Integrated circuit devices may utilize different types of circuit topologies for different applications. For example, some integrated circuit devices may utilize current mode logic (CML) circuits for high speed and/or low power applications. As will be understood by those skilled in the art, current mode logic (a/k/a source-coupled logic) is a differential digital logic family configured to transmit data at relatively high speeds. The transmission of data is typically point-to-point and unidirectional and terminated at a destination with 50Ω resistors to Vcc on differential lines. CML can be the physical layer used in DVI and HDMI video links, and is frequently used in interfaces to fiber optic components. CML has also been widely used in the design of high-speed integrated systems, such as in telecommunication systems (e.g., serial data transceivers, frequency synthesizers, etc.). The fast operation of CML circuits is mainly due to their lower output voltage swing compared to static CMOS circuits as well as the very fast current switching taking place at differential input transistors. Recently, CML topologies have been used in ultra-low power applications. Studies have shown that while the leakage current in conventional static CMOS circuits is becoming a major challenge in lowering energy dissipation, higher levels of control of current consumption in CML circuits may make them better candidates for low power applications. Thus, high-end clock circuits requiring very low phase noise and low current consumption may utilize CML cells.
Moreover, these CML cells must frequently be capable of operating correctly at extremes in the process corners, which frequently represent three or six sigma variations from nominal doping concentrations (and other parameters) in transistors on a silicon wafer. Among other things, these process variations can cause significant changes in the duty cycle and slew rate of digital signals and thereby limit the process yield of high performance circuits. Thus, while the nominal tail current of a CML cell may remain relatively constant independent of process corner, for the same operation frequency, a CML cell with a slow/fast process corner typically requires higher/lower tail current to perform well.
As will be understood by those skilled in the art, one naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P-channel MOSFET (PMOS) corner. Using this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal, respectively. Thus, a corner designated as FS denotes fast NFETs and slow PFETs.